1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, a static random access memory (static RAM or SRAM) in which the increase of the resistance due to a shift of alignment of a pattern during production can be prevented.
2. Description of the Related Art
SRAMs operate at a high speed and do not consume large electric power. From the view point of this low power consumption, SRAMs have extensively employed as memory devices in portable electronic (or electric) apparatuses such as a portable computer or moving electronic apparatus such as a moving portable small telephone. Since a power source of such portable electronic apparatus or moving electric apparatus is normally a battery (or a power cell), there is required a SRAM operable at a low voltage as low as possible and a low power consumption.
FIG. 1 is a circuit diagram of a SRAM in which a high resistance load or a thin film transistor (TFT) as an active load element of each of inverter circuits INV1 and INV2.
The SRAM shown in FIG. 1 comprises a bit memory cell formed at an intersection point of a bit line BL and a word line WL. The memory cell comprises a first inverter circuit INV1 and a second inverter circuit INV2. The first inverter circuit INV1 is formed by a load element HR1 formed by a high resistance load element or a TFT, and a driver transistor TR1. The second inverter circuit INV2 is also formed by a load element HR2 formed by a high resistance load element or a TFT, and a driver transistor TR2. The memory cell further comprises a first access (switching) transistor TR3 connected between the bit line BL and the word line WL, and a second access (switching) transistor TR4 connected between the bit line BL and the word line WL. The memory cell comprises a first resistance element R1 provided between a first node N1 of the first inverter circuit INV1 and the first access transistor TR3, and a second resistance element R2 provided between a second node N2 of the second inverter circuit INV2 and the second access transistor TR4.
In the memory cell, the high resistance loads HR1 and HR2 are provided as the active load elements of the first and second inverter circuits INV1 and INV2, but the TFTs can be provided as the active load elements.
In the memory cell, resistance elements R1 and R2 are provided as passive loads.
The access transistors TR3 and TR4 are energized to function as transfer gates to a memory portion of the memory cell, and thus these access transistors can be called as "transfer transistors" or merely "switching transistors".
FIG. 2 is a plan view of the memory cell of the SRAM shown in FIG. 1. Note, in FIG. 2, the layout (pattern) of only diffusion layer regions, gate electrodes formed by polycide, generally, and buried (or embedded) contacts, of the transistors TR1 to TR4 shown in FIG. 1, is illustrated. The bit line BL intersects the word line WL, but the bit line BL is formed at a layer different to another layer of the word line, and the bit line BL is not illustrated for simplifying the illustration.
The access transistor TR3 operatively connecting the bit line BL and the node N1 of the first inverter circuit INV1 is connected to a source (or drain) of the driver transistor TR1 of the first inverter circuit INV1 through a first connection diffusion layer region CDR1 a part of which forms the resistance element R1. The access transistor TR4 connecting the bit line BL and the node N2 of the second inverter circuit INV2 is connected to a source (or drain) of the driver transistor TR2 of the second inverter circuit INV2 through the second connection diffusion layer region CDR2 a part of which forms the resistance element R2.
The nodes N1 and N2, which are part of the diffusion layer regions CDR1 and CDR2, are respectively connected to gate electrodes PS2 and PS1 of the driver transistors TR2 and TR1 of the inverter circuits INV2 and INV1. The access transistors TR3 and TR4 are connected to the word line WL at shaded portions of the diffusion layer regions CDR1 and CDR2 in FIG. 2.
Sidewalls SW, illustrated by double lines in FIG. 2, are formed at circumference edges of the gate electrodes PS1 and PS2 and the word line WL. Birdbeaks BB are formed at boundary positions between the diffusion layers illustrated by dotted points in FIG. 2 and the field oxide layers.
During the production process of the SRAM shown in FIG. 2, an alignment of the driver transistors TR1 and TR2 and the gate electrodes PS1 and PS2 may be shifted.
The shift of the alignment by which the overlapping area of the first connection diffusion region CDR1 and the gate electrode PS2 will be increased, will be described.
A diffusion layer is not formed on the substrate positioned beneath the gate electrode PS2, but the concentration (density) of the diffusion layers of the substrate beneath the sidewalls SW which are formed as a LDD structure for a hot carrier countermeasure, is low. Therefore, if a portion of the connection diffusion layer region CDR1 forming the resistance element R1 and connecting the access transistor TR3 and the driver transistor TR1, which is pointed out by an arrow in FIG. 2, is shifted to the upper side as shown in FIG. 3, namely, the gate electrode PS2 is shifted to the upper side, the width of the connection diffusion layer region CDR1 becomes narrow to result in the increase of the resistance value thereat. This increase of the resistance means the increase of the resistance value of the resistance element R1, in the circuit of FIG. 1. The increase of the resistance value of the resistance element R1 disturbs the rise of the potential at the node N1 to a rated level. This disturbance of the rise of the potential requires a high voltage for raising the potential at the node N1 to the rated level. As a result, the SRAM does not operate at a low voltage.
Contrarily, if the gate electrode PS2 is shifted to the lower side in FIG. 2, the resistance value of the resistance element R2 will be increased to disturb the rise of the potential at the node N2 to a rated level. Consequently, the SRAM does not operate at a low voltage.
FIG. 4 is a plan view of another memory cell pattern of the SRAM shown in FIG. 1.
In FIG. 4, the access transistors TR3 and TR4 are connected by a second connection diffusion layer region 2CDR. The diffusion layer region 2CDR is connected to a bit line contact BC. The access transistor TR3 and the driver transistor TR1 of the inverter circuit INV1 are connected through a first connection diffusion layer region 1CDR.
In the SRAM shown in FIG. 4, the shift of the alignment, by which the overlapping area of the first connection diffusion layer region 1CDR and the gate electrode PS2 will be increased, may occur. When such shift of the alignment occurs the width of the first connection diffusion layer region 1CDR forming the resistance element R1 and connecting the access transistor TR3 and the driver transistor TR1 of the inverter circuit INV1 may be narrow and the resistance value thereat may be increased. That is, the resistance value of the resistance element R1 may be increased to disturb the rise of the potential at the node N1 of the inverter circuit INV1. The SRAM does not operate at a low level.
Contrary to the above, if the gate electrode PS2 is shifted to the lower side in FIG. 4, the resistance of the resistance element R2 may be increased to disturb the rise of the potential at the node N2. Consequently, the SRAM does not operate at a low voltage.